FPGA / DSP Engineer
Implement RF, radar, and sensor signal-processing pipelines on programmable silicon — where the math has to land in nanoseconds, not milliseconds.
Courses for this role
Foundations
Digital design, HDL, and the math that lets you implement DSP pipelines at line rate.
The two languages every FPGA engineer must read fluently.
State machines, pipelining, clock domains — the daily craft.
Real-time DSP almost never floats. Fixed-point fluency is the gate.
Building a CPU from gates up — best foundation in the discipline.
Build the stack
Vendor toolchains, HLS, and the production-grade FPGA flow used by defense primes.
The two vendor flows defense FPGA work happens in.
Designs that do not verify do not ship. UVM is the industry-standard verification methodology.
Ettus / NI USRP's open RF Network-on-Chip is the de facto framework for partitioning RF DSP between FPGA fabric and host. Critical for any FPGA engineer touching tactical SDR.
C++-to-RTL — increasingly how modern DSP pipelines are written.
FIR/IIR filters, FFTs, beamforming — at gigasamples per second.
Practical FPGA bring-up and verification.
The hardest single skill in production FPGA work.
Field experience
Hardware-in-loop, certified flows, and the radiation-hardened world of space-grade FPGA.
Validating FPGA behavior against real RF + sensors.
Recognized vendor credential.